1. Field of the Invention
The invention relates to a method for forming an offset spacer of a metal-oxide semiconductor (MOS) device.
2. Description of the Prior Art
As MOSFET and CMOS device characteristic sizes are scaled below 0.13 microns including below 0.1 micron, the process window for wet and dry etching processes are increasingly difficult to control to achieve desired critical dimensions. For example, in forming dielectric offset spacers, also referred to as sidewall spacers, the required width of the offset spacer is increasingly smaller. For example, the width of the offset spacer may be as small as 100 Angstroms (10 nanometers) or less in 65 nanometer characteristic dimensioned CMOS devices.
The offset spacer dielectric is formed adjacent either side of the gate structure and serves to allow the formation of source/drain extensions (SDE) or lightly doped drains (LDD). For instance, after the offset spacer is formed on the sidewall of the gate structure, a relatively lower amount of N or P-type doping is formed in the substrate adjacent to two sides of the offset spacer for forming lightly doped drain.
Offset spacer formation typically requires both deposition and etching processes, for example, to first deposit a single silicon oxide layer or a composite layer of a silicon oxide layer and a silicon nitride layer and subsequently remove portions of the deposited silicon oxide or silicon nitride layers. In conventional approach, the removal of portions of the deposited silicon oxide or silicon nitride layers is usually accomplished by a dry etching process, such as a plasma etching. However, plasma charging from the dry etching process not only penetrates the gate electrode to damage the gate oxide underneath, but also induces a silicon loss in the substrate adjacent to two sides of the offset spacer. It is therefore desirable to come up with a novel fabrication for improving the drawback caused by conventional approach.